Technical Field
The present invention relates to a test-used printed circuit board (PCB), and particularly to a test-used PCB having an in-series circuit involved with a join test action group (JTAG) signal.
Prior Art
For currently available test methods for slots, such as a memory slot and a peripheral component interconnect express (PCIE), a test-used printed circuit board (PCB) adopting a boundary scan technology is widely used.
However, when a test-used PCB is used, it has be correspondingly electrically connected to a joint test action group (JTAG) of a test access port (TAP). When a large of amounts of slots, such as a memory slot and a PCI (peripheral component interconnect) express slot, have to be concurrently tested, the JTAG ports of the TAP controller have to be largely used. However, since the number of the JTAG ports provided by the TAP is limited, the test for the memory slots and the PCI express slots may not be undertaken concurrently.
Although the number of the JTAG ports to be tested may be promoted by using an extension board of the TAP, the test-used PCB and the JTAG port of the TAP may involve a complexity and a confused corresponding relationship.
In view of the above, there have long been the issues of complexity and inconvenience for the slots on the PCB to be tested. Therefore, there is a need to set forth an improvement means to settle down this problem.